Back to Learning Paths
Intermediate
Design for Test
Make your chips testable — scan chains, ATPG, MBIST, and DFT flows.
8 modules ~64 min totalSynopsys DFT CompilerCadence Modus
Your Progress0%
0 of 8 completed
Curriculum Syllabus
All modules are open and public. Jump directly into what you need or follow in sequence.
1
Why Design for Test Exists
The importance of testability in manufactured chips.
2
Fault Models and Coverage
Understanding fault models and measuring test coverage.
3
Scan Design
Implementing scan chains for comprehensive test access.
4
ATPG: Generating the Patterns
Automatic Test Pattern Generation for stuck-at and transition faults.
5
Scan Compression
Reducing test time and data volume with scan compression.
6
Memory BIST
Built-in self-test for embedded memories.
7
Boundary Scan and JTAG
IEEE 1149.1 boundary scan for board-level testing.
8
DFT in the Design Flow
Integrating DFT into the overall chip design flow.
Companion Video Courses
Free NPTEL university lectures and full YouTube playlists that deepen this path.