Physical Design
From floorplan to tapeout — master the physical implementation of digital chips.
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Curriculum Syllabus
All modules are open and public. Jump directly into what you need or follow in sequence.
Introduction to Physical Design
Overview of the physical design flow and its role in chip implementation.
Floorplanning
Creating chip floorplans with macro placement and pin assignment.
Power Planning
Designing power distribution networks with rings, straps, and rails.
Placement
Standard cell placement and timing-driven placement optimization.
Clock Tree Synthesis (CTS)
Building balanced clock trees for minimal skew and insertion delay.
Routing
Signal routing with congestion and timing awareness.
Physical Verification
Running DRC, LVS, and ERC checks on the physical design.
PD Tool Knowledge
Key physical design tools and their capabilities.
Congestion Analysis and Fixes
Identifying and resolving routing congestion issues.
IR Drop and Power Integrity
Analyzing and fixing IR drop issues in power distribution.
The ECO Flow
Engineering Change Orders for late-stage design modifications.
Companion Video Courses
Free NPTEL university lectures and full YouTube playlists that deepen this path.
VLSI Physical Design
Prof. Indranil Sengupta · IIT Kharagpur
VLSI Design Flow: RTL to GDS
Prof. Sneh Saurabh · IIIT Delhi
VLSI Physical Design with Timing Analysis
Prof. Bishnu Prasad Das · IIT Roorkee
Advanced VLSI Design
Prof. A.N. Chandorkar, Prof. D.K. Sharma, Prof. Sachin Patkar, Prof. Virendra Singh · IIT Bombay
VLSI Design
Prof. A.N. Chandorkar · IIT Bombay
Design and Analysis of VLSI Subsystems
Prof. Madhav Rao · IIIT Bangalore
VLSI Physical Design Full Course
VLSI Academy · VLSI Academy