Practical Tapeout GuideSkyWater Sky130 PDK100% Open-Source EDA

OpenLane RTL-to-GDSII Complete Flow Walkthrough

A comprehensive, practical guide to implementing a real digital design from Verilog RTL to clean GDSII layout using OpenLane and the 130nm open-source PDK.

45 min deep dive 7 Flow Stages Industry Signoff Compliant

What is OpenLane?

OpenLane is an automated RTL to GDSII flow based on several open-source EDA components including Yosys, OpenROAD, Magic VLSI, Netgen, and OpenSTA. It performs full ASIC physical implementation without proprietary tool licenses, producing verified tapeout-ready GDSII layouts for manufacturing runs such as eFabless chipIgnite and Tiny Tapeout.

Frontend

Yosys + ABC

Logic synthesis, technology mapping, arithmetic inference

Physical Backend

OpenROAD

Floorplan, PDN, global placement, CTS, detailed routing

Signoff Verification

Magic + Netgen + OpenSTA

Design rule checks (DRC), layout vs. schematic (LVS), STA

Step-by-Step Flow Execution

Run either the interactive step-by-step flow or the one-line automated push-button flow.

Synthesis & Logic Optimization

Engine: Yosys + ABC

% run_synthesis

Translates high-level Verilog RTL into a gate-level netlist mapped to standard cells from the SkyWater Sky130 PDK. Analyzes gate count, area, and estimated timing.

Key Quality of Results (QoR) Metrics:

Gate count

Area (um²)

Timing WNS / TNS estimate

Flip-flop count

Floorplanning & IO Pin Placement

Engine: OpenROAD (init_floorplan)

% run_floorplan

Defines die and core boundaries, aspect ratio, utilization factor, core margins, and assigns IO pins along the chip perimeter based on user constraints.

Key Quality of Results (QoR) Metrics:

Core utilization (e.g. 45-55%)

Die area

IO pin pitch

Halo clearance

Power Distribution Network (PDN)

Engine: OpenROAD (pdn)

% run_power_grid

Builds power and ground grids (VDD/VSS rails and straps) across upper metal layers (met4, met5) to supply uniform current and minimize IR drop across the macro.

Key Quality of Results (QoR) Metrics:

Strap pitch & width

Rail connections

Worst-case IR drop target < 5%

Standard Cell Placement

Engine: OpenROAD (RePlace + OpenDP)

% run_placement

Performs global placement using force-directed algorithms to minimize wirelength, followed by legalization into standard cell rows without overlaps.

Key Quality of Results (QoR) Metrics:

Half-perimeter wire length (HPWL)

Overflow % < 0.1

Congestion heatmaps

Clock Tree Synthesis (CTS)

Engine: OpenROAD (TritonCTS)

% run_cts

Synthesizes balanced clock distribution networks using H-tree or multi-corner buffers to minimize clock skew and insertion delay across all sequential flip-flops.

Key Quality of Results (QoR) Metrics:

Clock skew < 150 ps

Max clock insertion delay

Max transition violations

Global & Detailed Routing

Engine: OpenROAD (FastRoute + TritonRoute)

% run_routing

Connects standard cell pins and clock trees across routing metal layers (met1 through met5), resolving design rule constraints (DRC) and inserting antenna diodes.

Key Quality of Results (QoR) Metrics:

DRC violation count = 0

Antenna violations = 0

Wirelength & via counts

Physical Verification & Signoff

Engine: Magic (DRC) + Netgen (LVS) + OpenSTA

% run_magic; run_lvs; run_magic_gds

Runs signoff DRC checks against manufacturing rules, extracts the layout netlist, verifies schematic-versus-layout (LVS) equivalence, and generates the final GDSII stream.

Key Quality of Results (QoR) Metrics:

DRC Clean (0 errors)

LVS Match (Netlists identical)

Final STA Slack (Setup & Hold >= 0)

config.json — Sky130 Standard Macro ConfigurationJSON Configuration

{
  "DESIGN_NAME": "picorv32a",
  "VERILOG_FILES": "dir::src/picorv32a.v",
  "CLOCK_PORT": "clk",
  "CLOCK_PERIOD": 10.0,
  "DESIGN_IS_CORE": 0,
  "FP_SIZING": "relative",
  "FP_CORE_UTIL": 45,
  "PL_TARGET_DENSITY": 0.48,
  "PL_BASIC_PLACEMENT": 0,
  "CTS_TARGET_SKEW": 0.15,
  "GLB_RT_MAXLAYER": 5,
  "ROUTING_CORES": 4,
  "RUN_MAGIC": 1,
  "RUN_KLAYOUT": 1,
  "RUN_LVS": 1,
  "RUN_CVC": 1
}

Note: CLOCK_PERIOD is specified in nanoseconds (10.0 ns = 100 MHz target). FP_CORE_UTIL is set to 45% to leave sufficient routing tracks for detailed routing without congestion hot-spots.

Common Tapeout Bottlenecks & Fixes

1. Routing Congestion / DRC Exploding

Symptom: Detailed router reports hundreds of short / spacing violations on met2 and met3.
Fix: Lower FP_CORE_UTIL from 50% to 40-42%, or reduce PL_TARGET_DENSITY to 0.45. Ensure standard cell halo clearance around macros is set to at least 10 um.

2. Hold Time Violations Post-Routing

Symptom: Negative slack on min/fast corner after detailed routing due to clock tree insertion delay variations.
Fix: Enable hold buffer insertion via PL_RESIZER_HOLD_SLACK_MARGIN: 0.1 and verify multi-corner CTS with CTS_CLK_BUFFER_LIST using matched inverter pairs.

3. LVS Pin / Port Discrepancies

Symptom: Netgen reports unmatched nets or missing supply connections (VDD/VSS).
Fix: Verify that VDD_NETS and GND_NETS explicitly list vccd1 and vssd1 for Sky130 standard cells. Ensure tie-high and tie-low cells are inserted properly.

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