Signoff Diagnostics
Engineering Lab: Violation Case Studies
Inspect real EDA log excerpts from Synopsys PrimeTime, Cadence Innovus, and Tempus. Learn the exact reasoning used by physical design and signoff engineers to diagnose and resolve tapeout violations.
Setup Timing Violation
Domain: core_clock_clk (1 GHz)
WNS
−143 ps
TNS
−2.84 ns
Logic Depth
18 levels
Corner
ss/0.72V/125°C
PrimeTime :: report_timing -delay_type max -nworst 1
RAW LOG EXCERPTPath Group: core_clock_clk Startpoint: reg_124 (rising edge-triggered flip-flop) Endpoint: reg_892 (rising edge-triggered flip-flop) Analysis Corner: ss/0.72V/125°C (Worst Setup PVT) Point Incr Path ------------------------------------------------------------- clock clk (rise edge) 0.000 0.000 clock network delay (propagated) 0.120 0.120 reg_124/CLK 0.000 0.120 r reg_124/Q (DFFHQ4X1) 0.115 0.235 f u_alu/adder_18/S 1.798 2.033 r (18 levels) u_mux/out 0.110 2.143 f data arrival time 2.143 clock clk (rise edge) 2.000 2.000 clock network delay (propagated) 0.090 2.090 clock reconvergence pessimism 0.012 2.102 clock uncertainty -0.080 2.022 reg_892/CLK 0.000 2.022 r library setup time -0.132 1.890 data required time 1.890 ------------------------------------------------------------- slack (VIOLATED) -0.143 ns
Diagnostic Question
“Your design passes timing cleanly before CTS. After CTS, setup slack is violated by −143 ps. What is the root cause and diagnostic procedure?”