Verilog
Learn Verilog from scratch — from your first module to synthesizable RTL design.
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Curriculum Syllabus
All modules are open and public. Jump directly into what you need or follow in sequence.
What Verilog Really Is
Introduction to Verilog as a hardware description language and its role in chip design.
Your First Module
Writing your first Verilog module with inputs, outputs, and behavioral modeling.
Wires, Regs, and the Four Values
Understanding wire and reg data types and the four-state logic values.
Operators You Will Actually Use
Essential Verilog operators for bitwise, logical, and arithmetic operations.
Combinational Logic
Modeling combinational logic with continuous assignments and always blocks.
if, case, and Avoiding Latches
Using if-else and case statements while avoiding unintended latches.
Sequential Logic and the Clock
Sequential logic design with clocked always blocks and edge detection.
Blocking vs Non-blocking
Understanding blocking (=) and non-blocking (<=) assignments and when to use each.
Finite State Machines
Designing FSMs in Verilog with state encoding and transition logic.
Writing a Testbench
Creating testbenches to verify Verilog designs with stimulus and checks.
Synthesizable RTL and Next Steps
Writing synthesizable RTL and preparing for synthesis tools.
Parameters and Generate
Using parameters and generate statements for scalable Verilog designs.
Common RTL Building Blocks
Reusable RTL patterns: FIFOs, arbiters, and pipeline registers.
From Verilog to SystemVerilog
Transitioning from Verilog to SystemVerilog for modern design and verification.
Companion Video Courses
Free NPTEL university lectures and full YouTube playlists that deepen this path.
Hardware modeling using verilog
Prof. Indranil Sengupta · IIT Kharagpur
System Design Through VERILOG
Prof. Shaik Rafi Ahamed · IIT Guwahati
C-Based VLSI Design
Prof. Chandan Karfa · IIT Guwahati
VHDL Programming
Neso Academy · Neso Academy