Synthesis
Transform RTL into gates — master the synthesis flow from constraints to QoR.
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Curriculum Syllabus
All modules are open and public. Jump directly into what you need or follow in sequence.
Introduction to Synthesis
What synthesis is and how it fits into the chip design flow.
Detailed Synthesis Flow
Step-by-step synthesis process from RTL to gate-level netlist.
Synopsys Design Compiler (DC)
Using Design Compiler for logic synthesis and optimization.
Cadence Genus
Introduction to Cadence Genus synthesis tool.
Timing Constraints (SDC)
Writing Synopsys Design Constraints for timing and area.
Optimization Techniques
Key optimization strategies in synthesis for timing and area.
Quality of Results (QoR)
Evaluating synthesis quality through timing, area, and power metrics.
Retiming: Moving Registers to Balance Logic
Using retiming to improve timing by redistributing registers.
Hierarchy: Ungroup, Flatten, and Boundary Optimization
Managing design hierarchy for optimal synthesis results.
Power-Aware Synthesis: Clock Gating and Multi-Vt
Techniques for reducing power consumption during synthesis.
DFT and Scan-Aware Synthesis
Integrating design-for-test structures during synthesis.
Companion Video Courses
Free NPTEL university lectures and full YouTube playlists that deepen this path.