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Intermediate
Clock Domain Crossing
Safely transfer data between clock domains — from metastability to async FIFOs.
8 modules ~68 min total
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Curriculum Syllabus
All modules are open and public. Jump directly into what you need or follow in sequence.
1
Why Clock Domain Crossing Matters
Understanding the challenges of multi-clock domain designs.
2
Metastability, Explained
Deep dive into metastability, MTBF, and why it happens.
3
The Two-Flop Synchronizer
Implementing and analyzing the two-flop synchronizer for single-bit signals.
4
Buses and Gray Code
Using Gray code for safe multi-bit CDC across clock domains.
5
The Asynchronous FIFO
Designing async FIFOs with Gray code pointers for reliable data transfer.
6
Handshake and Pulse Synchronizers
Alternative CDC techniques using handshakes and pulse synchronizers.
7
Reset Synchronization
Synchronizing reset signals across clock domains.
8
CDC Verification and Common Mistakes
Techniques for verifying CDC correctness and common pitfalls to avoid.